During the fabrication of integrated circuits such as memory devices, it is conventional to test such integrated circuits at several stages during the fabrication process. For example, after fabrication, integrated circuits may be connected to a tester with a probe card when the integrated circuits are still in wafer form. In a final test occurring after the integrated circuits have been diced from the wafer and packaged, the integrated circuits may be placed into sockets on a load board or other device and once again tested.
As is well-known in the art, memory devices may be provided with circuitry that allows limited repair of defects in the memory devices. Such repair devices may allow defects to be repaired at specific addresses. Once the addresses that include a defect have been determined (i.e., once the address at which respective defects are located have been obtained by testing), the defects may then be repaired.
Memory devices are conventionally tested during fabrication and after packaging using high-speed automated testers. The testers typically having a single data input/output (“I/O”) bus, which is normally coupled to several memory devices during a test. Although data may be simultaneously written to all of the memory devices, data may not be simultaneously read from all of the memory devices or else several memory devices may simultaneously apply read data to the I/O bus of the tester. To avoid this bus contention problem, data may be read from each of the memory devices in sequence, thereby requiring multiple read cycles to read the data from all of the memory devices. Further, conventional testers for memory devices are very expensive, and using a separate tester to test each memory device individually would require a very large number of testers in a high volume memory device fabrication environment. To limit the cost of memory device testing, memory testers may test a large number of devices in parallel. In these situations, a tester may transmit write commands, addresses and data to a large number of memory devices in parallel, thus writing the same data to the same locations in all of the memory devices. The memory devices may then read to determine if the read data matches the write data. If the data read at any address does not match the data written to that address, then a defect at that address is considered to exist.
One problem with testing memory devices using the above-described techniques is that it may be necessary to read data from each memory device individually to determine if data read from each address is in error. Doing so can greatly limit the rate at which a tester can test memory devices. As a result, attempts have been made to provide memory devices with limited on-board test capabilities. One approach has been to provide comparison circuitry in the memory device itself to avoid the need to couple read data from the memory device for evaluation. A large number of memory devices may be coupled to a tester in parallel. The tester may simultaneously write data to each address in all of the memory devices, and the memory device subsequently compares the data written to each address with the data read from that address. In another approach, bits of the data read responsive to a memory request may be compared to each other to detect and error, or the correct comparison bits may be supplied to the memory devices by the tester with the read commands. In any case, a bit indicative of an error can be stored in an on-board storage device, such as a latch. Address bits corresponding to the location of the defect causing the error can also be stored in an on-board storage device. The on-board storage devices can then be read at the conclusion of the test to determine the addresses where errors have been detected, and those addresses can then be repaired by conventional means. Unfortunately, it can require a significant number of storage devices, such as latches, to store all of the address bits for each of a large number of addresses that are to be repaired by conventional means. As a result, the storage capacity and/or cost of memory devices can be adversely affected by the need to provide a large amount of circuitry to store error data.